SH7641 Datasheet, PDF (342/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Bit
5 to 2
1
0
Bit Name

Initial
Value
All 0
HW1
0
HW0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Delay Cycles from RD, WEn Negation to Address, CSn
R/W ^Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5AWCR
Bit
Bit Name
31 to 19 
Initial
Value
All 0
18
WW2
0
17
WW1
0
16
WW0
0
15 to 13 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Write Access Wait Cycles
R/W Specify the number of cycles that are necessary for
R/W ^{write access.}
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 292 of 982
REJ09B0023-0400