SH7641 Datasheet, PDF (70/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 1 Overview
Classification
Bus control
Symbol
I/O
RD/WR
O
BS
O
WE3/DQMUU/ O
AH
WE2/DQMUL O
WE1/DQMLU O
WE0/DQMLL O
RASU, RASL O
CASU, CASL O
CKE
O
FRAME
O
WAIT
I
Name
Function
Read/write
Read/write signal
Bus start
Bus-cycle start
Byte specification Indicates that bits 31 to 24 of the
data in the external memory or
device are being written.
Selects D31 to D24 when SDRAM is
connected.
Address hold signal for address/data
multiplexed I/O.
Byte specification Indicates that bits 23 to 16 of the
data in the external memory or
device are being written.
Selects D23 to D16 when SDRAM is
connected.
Byte specification Indicates that bits 15 to 8 of the data
in the external memory or device are
being written.
Selects D15 to D8 when SDRAM is
connected.
Byte specification Indicates that bits 7 to 0 of the data
in the external memory or device are
being written.
Selects D7 to D0 when SDRAM is
connected.
RAS
Connected to the RAS pin when the
SDRAM is connected.
CAS
Connected to the CAS pin when the
SDRAM is connected.
CK enable
Connected to the CKE pin when the
SDRAM is connected.
FRAME signal
Connects the FRAME signal for the
burst MPX-IO interface.
Wait
When active, inserts a wait cycle into
the bus cycles during access to the
external space.
Rev. 4.00 Sep. 14, 2005 Page 20 of 828
REJ09B0023-0400