SH7641 Datasheet, PDF (122/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction
MOV.L Rm,@(R0,Rn)
MOV.B @(R0,Rm),Rn
MOV.W @(R0,Rm),Rn
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
@(R0,Rm),Rn
R0,@(disp,GBR)
R0,@(disp,GBR)
R0,@(disp,GBR)
@(disp,GBR),R0
MOV.W @(disp,GBR),R0
MOV.L @(disp,GBR),R0
MOVA @(disp,PC),R0
MOVT Rn
SWAP.B Rm,Rn
SWAP.W Rm,Rn
XTRCT Rm,Rn
Instruction Code
0000nnnnmmmm0110
0000nnnnmmmm1100
0000nnnnmmmm1101
0000nnnnmmmm1110
11000000dddddddd
11000001dddddddd
11000010dddddddd
11000100dddddddd
11000101dddddddd
11000110dddddddd
11000111dddddddd
0000nnnn00101001
0110nnnnmmmm1000
0110nnnnmmmm1001
0010nnnnmmmm1101
Operation
Execution
States
Rm → (R0 + Rn)
1
(R0 + Rm) → Sign extension 1
→ Rn
(R0 + Rm) → Sign extension 1
→ Rn
(R0 + Rm) → Rn
1
R0 → (disp + GBR)
1
R0 → (disp × 2 + GBR)
1
R0 → (disp × 4 + GBR)
1
(disp + GBR) → Sign
1
extension → R0
(disp × 2 + GBR) →
1
Sign extension → R0
(disp × 4 + GBR) → R0
1
disp × 4 + PC → R0
1
T → Rn
1
Rm → Swap lowest two
1
bytes → Rn
Rm → Swap two consecutive 1
words → Rn
Middle 32 bits of Rm and 1
Rn → Rn
T Bit
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Rev. 4.00 Sep. 14, 2005 Page 72 of 982
REJ09B0023-0400