SH7641 Datasheet, PDF (471/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
13.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1)
DMARS is a 16-bit read/write register that specifies the DMA transfer sources from peripheral
modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies for
channels 2 and 3. This register can set the transfer request of SCIF0, SCIF1, SCIF2, MTU0,
MTU1, MTU2, MTU3, MTU4, MTU, USB, A/D converter 1, and CMT1.
This register is initialized to H'0000 by power-on manual reset. The previous value is held in
standby mode or module standby mode.
• DMARS0
Bit
Bit Name
15
C1MID5
14
C1MID4
13
C1MID3
12
C1MID2
11
C1MID1
10
C1MID0
9
C1RID1
8
C1RID0
7
C0MID5
6
C0MID4
5
C0MID3
4
C0MID2
3
C0MID1
2
C0MID0
1
C0RID1
0
C0RID0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Description
R/W Transfer request module ID5 for DMA channel 1 (MID).
R/W ^{See table 13.3.}
R/W
R/W
R/W
R/W
R/W Transfer request register ID for DMA channel 1 (RID).
R/W ^{See table 13.3.}
R/W Transfer request module ID for DMA channel 0 (MID).
R/W ^{See table 13.3}
R/W
R/W
R/W
R/W
R/W Transfer request register ID for DMA channel 0 (RID).
R/W ^{See table 13.3.}
Rev. 4.00 Sep. 14, 2005 Page 421 of 982
REJ09B0023-0400