SH7641 Datasheet, PDF (239/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 7 Cache
7.3.5 Write-Back Buffer
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the cache completes to fetch the new entry, the write-back buffer writes
the entry back to external memory. During the write-back cycles, the cache can be accessed. The
write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 7.3
shows the configuration of the write-back buffer.
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4): Physical address written to external memory
Longword 0 to 3: The line of cache data to be written to external memory
Figure 7.3 Write-Back Buffer Configuration
7.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is mapped in the address space to be cached, operate the
memory mapped cache to invalidate and write back as required.
Rev. 4.00 Sep. 14, 2005 Page 189 of 982
REJ09B0023-0400