SH7641 Datasheet, PDF (284/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
Edge input interrupt detection requires input of a pulse width of more than two cycles on a P clock
basis.
When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU
samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt
handling.
10.4.4 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following 9 modules:
• DMA controller (DMAC)
• Serial communication interfaces (SCIF0 to SCIF2)
• A/D converters (ADC0 and ADC1)
• Compare match timers (CMT0 and CMT1)
• USB function module (USB)
• Multifunction timer pulse units (MTU0 to MTU4)
• Watchdog timer (WDT)
• User debugging interface (H-UDI)
• I²C bus interface 2 (IIC2)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event register (INTEVT2). It is easy to identify sources by using the value of the
INTEVT2 register as a branch offset.
A priority level (from 0 to 15) can be set for each module except H-UDI by writing to interrupt
priority registers B to J (IPRB to IPRJ). The priority level of the H-UDI interrupt is 15 (fixed).
The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral
module interrupt handling.
Rev. 4.00 Sep. 14, 2005 Page 234 of 982
REJ09B0023-0400