SH7641 Datasheet, PDF (189/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
/* The value to be added to the address register depends on addressing
instructions.
For example, (+2 or R8[Ix] or +0) means that
+2:
if instruction is increment
R8[Ix]: if instruction is add-index-register
+0:
if instruction is not-update
*/
function modulo ( AddrReg, Index ) {
if ( AddrReg[15:1]==ME[15:1] ) AddrReg[15:1]==MS[15:1];
else AddrReg=AddrReg+Index;
return AddrReg;
}
X and Y Data Transfer Instructions (MOVX.W and MOVY.W): This type of instruction uses
the XDB and the YDB to access X and Y data memories (they cannot access other memory
spaces). These two buses are separate from the instruction bus, therefore, there is no access
conflict between data memory access and instruction memory access.
Figure 3.22 shows load/store control for X and Y data transfer instructions. All memory accesses
are word mode accesses.
Rev. 4.00 Sep. 14, 2005 Page 139 of 982
REJ09B0023-0400