SH7641 Datasheet, PDF (627/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
The correspondence between PWM output pins and registers is shown in table 18.31.
Table 18.31 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGRA_0
TIOC0A
TIOC0A
TGRB_0
TIOC0B
TGRC_0
TIOC0C
TIOC0C
TGRD_0
TIOC0D
1
TGRA_1
TIOC1A
TIOC1A
TGRB_1
TIOC1B
2
TGRA_2
TIOC2A
TIOC2A
TGRB_2
TIOC2B
3
TGRA_3
TIOC3A
Setting prohibited
TGRB_3
Setting prohibited
TGRC_3
TIOC3C
Setting prohibited
TGRD_3
Setting prohibited
4
TGRA_4
TIOC4A
Setting prohibited
TGRB_4
Setting prohibited
TGRC_4
TIOC4C
Setting prohibited
TGRD_4
Setting prohibited
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Rev. 4.00 Sep. 14, 2005 Page 577 of 982
REJ09B0023-0400