SH7641 Datasheet, PDF (121/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Data Transfer Instructions
Table 2.19 Data Transfer Instructions
Instruction
MOV
#imm,Rn
MOV.W @(disp,PC),Rn
MOV.L
MOV
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
@(disp,PC),Rn
Rm,Rn
Rm,@Rn
Rm,@Rn
Rm,@Rn
@Rm,Rn
@Rm,Rn
@Rm,Rn
Rm,@–Rn
Rm,@–Rn
Rm,@–Rn
@Rm+,Rn
MOV.W @Rm+,Rn
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
@Rm+,Rn
R0,@(disp,Rn)
R0,@(disp,Rn)
Rm,@(disp,Rn)
@(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L
MOV.B
MOV.W
@(disp,Rm),Rn
Rm,@(R0,Rn)
Rm,@(R0,Rn)
Instruction Code
1110nnnniiiiiiii
1001nnnndddddddd
1101nnnndddddddd
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
0110nnnnmmmm0101
0110nnnnmmmm0110
10000000nnnndddd
10000001nnnndddd
0001nnnnmmmmdddd
10000100mmmmdddd
10000101mmmmdddd
0101nnnnmmmmdddd
0000nnnnmmmm0100
0000nnnnmmmm0101
Operation
Execution
States
imm → Sign extension → Rn 1
(disp × 2 + PC) → Sign
1
extension → Rn
(disp × 4 + PC) → Rn
1
Rm → Rn
1
Rm → (Rn)
1
Rm → (Rn)
1
Rm → (Rn)
1
(Rm) → Sign extension → Rn 1
(Rm) → Sign extension → Rn 1
(Rm) → Rn
1
Rn–1 → Rn, Rm → (Rn)
1
Rn–2 → Rn, Rm → (Rn)
1
Rn–4 → Rn, Rm → (Rn)
1
(Rm) → Sign extension → Rn, 1
Rm + 1 → Rm
(Rm) → Sign extension → Rn, 1
Rm + 2 → Rm
(Rm) → Rn,Rm + 4 → Rm
1
R0 → (disp + Rn)
1
R0 → (disp × 2 + Rn)
1
Rm → (disp × 4 + Rn)
1
(disp + Rm) → Sign
1
extension → R0
(disp × 2 + Rm) → Sign
1
extension → R0
(disp × 4 + Rm) → Rn
1
Rm → (R0 + Rn)
1
Rm → (R0 + Rn)
1
T Bit
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Rev. 4.00 Sep. 14, 2005 Page 71 of 982
REJ09B0023-0400