SH7641 Datasheet, PDF (133/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 2 CPU
Instruction
STS.L DSR,@-Rn
STS.L A0,@-Rn
STS.L X0,@-Rn
STS.L X1,@-Rn
STS.L Y0,@-Rn
STS.L Y1,@-Rn
STC.L MOD,@-Rn
STC.L RS,@-Rn
STC.L RE,@-Rn
LDS.L @Rn+,DSR
LDS.L @Rn+,A0
LDS.L @Rn+,X0
LDS.L @Rn+,X1
LDS.L @Rn+,Y0
LDS.L @Rn+,Y1
LDC.L @Rn+,MOD
LDC.L @Rn+,RS
LDC.L @Rn+,RE
LDS Rn,DSR
LDS Rn,A0
LDS Rn,X0
LDS Rn,X1
LDS Rn,Y0
LDS Rn,Y1
LDC Rn,MOD
LDC Rn,RS
LDC Rn,RE
Instruction Code
0100nnnn01100010
0100nnnn01110010
0100nnnn10000010
0100nnnn10010010
0100nnnn10100010
0100nnnn10110010
0100nnnn01010011
0100nnnn01100011
0100nnnn01110011
0100nnnn01100110
0100nnnn01110110
0100nnnn10000110
0100nnnn10010110
0100nnnn10100110
0100nnnn10110110
0100nnnn01010111
0100nnnn01100111
0100nnnn01110111
0100nnnn01101010
0100nnnn01111010
0100nnnn10001010
0100nnnn10011010
0100nnnn10101010
0100nnnn10111010
0100nnnn01011110
0100nnnn01101110
0100nnnn01111110
Operation
Rn – 4 → Rn, DSR → (Rn)
Rn – 4 → Rn, A0 → (Rn)
Rn – 4 → Rn, X0 → (Rn)
Rn – 4 → Rn, X1 → (Rn)
Rn – 4 → Rn, Y0 → (Rn)
Rn – 4 → Rn, Y1 → (Rn)
Rn – 4 → Rn, MOD → (Rn)
Rn – 4 → Rn, RS → (Rn)
Rn – 4 → Rn, RE → (Rn)
(Rn) → DSR, Rn + 4 → Rn
(Rn) → A0, Rn + 4 → Rn
(Rn) → X0, Rn + 4 → Rn
(Rn) → X1, Rn + 4 → Rn
(Rn) → Y0, Rn + 4 → Rn
(Rn) → Y1, Rn + 4 → Rn
(Rn) → MOD, Rn + 4 → Rn
(Rn) → RS, Rn + 4 → Rn
(Rn) → RE, Rn + 4 → Rn
Rn → DSR
Rn → A0
Rn → X0
Rn → X1
Rn → Y0
Rn → Y1
Rn → MOD
Rn → RS
Rn → RE
Execution
States T Bit
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

4

4

4

1

1

1

1

1

1

4

4

4

Rev. 4.00 Sep. 14, 2005 Page 83 of 982
REJ09B0023-0400