SH7641 Datasheet, PDF (498/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CPU
1st acceptance
Non-sensitive period
DMAC write
2nd acceptance 3rd acceptance possible
Non-sensitive period
CKIO
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(High-active)
CPU
DMAC write
1st acceptance
2nd acceptance 3rd acceptance possible
Non-sensitive period Non-sensitive period
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
When DACK is Divided to 4 by Idle Cycles
Rev. 4.00 Sep. 14, 2005 Page 448 of 982
REJ09B0023-0400