SH7641 Datasheet, PDF (860/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 21 A/D Converter
21.3.5 A/D Converter Activation by MTU
The A/D converter can be independently activated by an A/D conversion request from the MTU or
CSL.
To activate the A/D converter by the MTU, set the A/D trigger enable bit (TRGE). After this bit
setting has been made, the ADST bit in ADCSR is automatically set to 1 and A/D conversion is
started when an A/D conversion request from the MTU occurs. If the TRGE bit in both ADCSR0
and ADCSR1 is set to 1, starts simultaneous sampling of two channels. Channels for sampling are
determined by the CH1 and CH0 bits of the ADCSR0 or ADCSR1. The timing from setting of the
ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by
software.
21.3.6 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 21.5 shows the A/D
conversion timing. Table 21.3 indicates the A/D conversion time.
As indicated in figure 21.5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 21.3.
In multi mode and scan mode, the values given in table 21.3 apply to the first conversion. In the
second and subsequent conversions time is the values given in table21.4.
Rev. 4.00 Sep. 14, 2005 Page 810 of 982
REJ09B0023-0400