SH7641 Datasheet, PDF (896/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 23 I/O Ports
23.2.2 Port B Data Register (PBDR)
PBDR is a 9-bit readable/writable register with seven reserved bits that stores data for pins PTB8
to PTB0. PBDR is initialized to H'0000 by a power-on reset, but it retains its previous value by a
manual reset, in standby mode, or in sleep mode.
Bit
15 to 9
Bit Name

7
PB7DT
6
PB6DT
5
PB5DT
4
PB4DT
3
PB3DT
2
PB2DT
1
PB1DT
0
PB0DT
Initial
Value
All 0
0
0
0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Bits PB8DT to PB0DT correspond to pins PTB8 to
R/W ^{PTB0. When the pin function is general output port, the}
value of the corresponding bit in PBDR is returned
R/W _{directly by reading the port. When the function is}
R/W ^{general input port, the corresponding pin level is read}
by reading the port. Table 23.2 shows the function of
R/W _PBDR.
R/W
R/W
R/W
Table 23.2 Port B Data Register (PBDR) Read/Write Operations
PBnMD2 PBnMD1 Pin State
0
0
Input
Read
Pin state
1
Output
PBDR value
1
0
Reserved

1
Other functions Pin state
(n = 0 to 8)
Write
Data is written to PBDR, but does not affect
pin state.
Data is written to PBDR and the value is
output from the pin.

Data is written to PBDR, but does not affect
pin state.
Rev. 4.00 Sep. 14, 2005 Page 846 of 982
REJ09B0023-0400