SH7641 Datasheet, PDF (502/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 14 U Memory
14.2 U Memory Access from CPU
The U memory can be accessed by the CPU from spaces P0 and P2. Access from the CPU is via
the I bus when U memory is space P0, and via the L bus when space P2. To use the L bus, one
cycle access is performed unless page conflict occurs. Using the I bus takes more than one cycle.
Address A[28:0]
H'04000000
H'05000000
H'0501FFFF
H'055F0000
H'0560FFFF
H'05610000
Area1, 64 Mbytes
I/O space
16 Mbytes
X/Y memory
Reserved
Reserved
Address A[28:0]
H'055F0000
H'055FFFFF
H'05600000
H'0560FFFF
U memory space
U memory page0
64 kbytes
U memory page1
64 kbytes
H'07FFFFFF
Figure 14.1 U Memory Address Mapping
14.3 U Memory Access from DSP
The DSP can access the U memory through spaces P0 and P2 using a single data transfer
instruction. Access from the DSP is via the I bus when the address is space P0, and via the L bus
when the address is space P2. To use the L bus, one cycle access is performed unless page conflict
occurs. Using the I bus takes more than one cycle.
14.4 U Memory Access from DMAC
The U memory also exists on the I bus and can be accessed by the DMAC. Use addresses
H'55F0000 to H'560FFFF.
Rev. 4.00 Sep. 14, 2005 Page 452 of 982
REJ09B0023-0400