SH7641 Datasheet, PDF (407/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Single Write: A write access ends in one cycle when data is written in non-cacheable region and
the data bus width is larger than or equal to access size.
Figure 12.22 shows the single write basic timing.
CKIO
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1 Trwl
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.22 Single Write Basic Timing (Auto-Precharge)
Rev. 4.00 Sep. 14, 2005 Page 357 of 982
REJ09B0023-0400