SH7641 Datasheet, PDF (604/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.8 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
Bit
7
6
5 to 3
2
1
0
Bit Name
CST4
CST3
Initial
value
0
0

All 0
CST2
0
CST1
0
CST0
0
R/W Description
R/W Counter Start 4 and 3
R/W These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Counter Start 2 to 0
R/W These bits select operation or stoppage for TCNT.
R/W If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_2 and TCNT_0 count operation is stopped
1: TCNT_2 and TCNT_0 performs count operation
18.3.9 Timer Synchro Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Rev. 4.00 Sep. 14, 2005 Page 554 of 982
REJ09B0023-0400