SH7641 Datasheet, PDF (354/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Bit
Bit Name
17
BW1
16
BW0
15 to 13 
12
SW1
11
SW0
Initial
Value
0
0
All 0
0
0
R/W Description
R/W Number of Burst Wait Cycles
R/W Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Delay Cycles from Address, CSn Assertion
R/W ^{to RD, WE Assertion}
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 4.00 Sep. 14, 2005 Page 304 of 982
REJ09B0023-0400