SH7641 Datasheet, PDF (614/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT value
H'FFFF
H'0000
CST bit
TCFV
Time
Figure 18.4 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The TGR register for setting the period is designated
as an output compare register, and counter clearing by compare match is selected by means of bits
CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as
a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches
the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt.
After a compare match, TCNT starts counting up again from H'0000.
Figure 18.5 illustrates periodic counter operation.
TCNT value
TGR
Counter cleared by TGR
compare match
H'0000
CST bit
TGF
Time
Flag cleared by software or
DMA activation
Figure 18.5 Periodic Counter Operation
• Waveform Output by Compare Match
The MTU can perform 0, 1, or toggle output from the corresponding output pin using compare
match.
Rev. 4.00 Sep. 14, 2005 Page 564 of 982
REJ09B0023-0400