SH7641 Datasheet, PDF(173/1036 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7641 Datasheet, PDF (173/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

◁

Section 3 DSP Operation

3.1.11 Operand Conflict

When an identical destination operand is specified with multiple parallel instructions, data conflict

occurs. Table 3.14 shows the correspondence between each operand and registers.

Table 3.14 Correspondence between Operands and Registers

X-Memory

Load

Y-Memory 6-Instruction 3-Instruction 3-Instruction

Load

ALU

Multiply

ALU

Ax Ix Dx Ay Iy Dy Sx Sy Du Se Sf Dg Sx Sy Dz

DSP

A0

Registers A1

M0

M1

X0

X1

Y0

Y1

*1

*2

*2 *1

*1

*1

*2 *1 *1 *2 *1

*1

*1

*1

*1 *1

*1

*1

*1 *1

*2

*1

*2 *1 *1

*1

*2

*2

*1

*1

*1

*2

*2

*1 *2 *1 *1

*1 *2

*2

*1

*1

*1 *2

Notes: 1. Registers available for operands

2. Registers available for operands (when there is operand conflict)

There are three cases of operand conflict problems.

1. When ALU and multiply instructions specify the same destination operand (Du and Dg)

2. When X-memory load and ALU instructions specify the same destination operand (Dx, Du,

and Dz)

3. When Y-memory load and ALU instructions specify the same destination operand (Dy, Du,

and Dz)

In these cases above, the result is not guaranteed.

Rev. 4.00 Sep. 14, 2005 Page 123 of 982

REJ09B0023-0400

▷