SH7641 Datasheet, PDF (783/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Start
1 bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
Serial
data
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0
0/1
RDF
FER
One frame
RXI interrupt
request
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 19.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)
5. When modem control is enabled, the RTS signal is output depending on the empty status of
SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR
exceeds the number set for the RTS output active trigger.
Figure 19.10 shows an example of the operation when modem control is used.
Serial data
RxD
Start
bit
0 D0 D1 D2
Parity Stop
bit bit
D7 0/1 1
Start
bit
0 D0 D1
D7 0/1
RTS
Figure 19.10 Example of Operation Using Modem Control (RTS)
19.4.3 Synchronous Operation
In synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCIF transmitter and receiver are independent, so full-duplex communication is possible
while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Rev. 4.00 Sep. 14, 2005 Page 733 of 982
REJ09B0023-0400