SH7641 Datasheet, PDF (335/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10
BSZ1
1*
R/W Data Bus Size
9
BSZ0
1*
R/W Specify the data bus sizes of spaces.
The data bus sizes of areas 2, 3, 4 and 5A are shown
below.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size
For MPX-I/O, selects bus width by address
Notes: 1. If area 5B is specified as MPX-I/O, the bus
width can be specified as 8 bits or 16 bits by
the address according to the SZSEL bit in
CS5BWCR by specifying these bits to 11.
2. The data bus width for area 0 is specified by
the external pin. The BSZ1 and BSZ0 bit
settings in the CS0BCR register are
ignored.
3. If area 6 is specified as burst MPX-I/O, the
bus width can be specified as 32 bits only.
4. If area 2 or area 3 is specified as SDRAM
space, the bus width can be specified as
either 16 bits or 32 bits.
8 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * The CS0CR samples the external pins (MD3) that specify the bus width at power-on
reset.
Rev. 4.00 Sep. 14, 2005 Page 285 of 982
REJ09B0023-0400