SH7641 Datasheet, PDF (475/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Figure 13.2 is a flowchart of this procedure.
Section 13 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR,
DMAOR, DMARS)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and
DAR updated
*²
*³
Bus mode,
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
TE = 1
DEI interrupt request (when IE = 1)
NMIF = 1
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer end
No
Normal end
NMIF = 1
No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer aborted
Notes: 1.
2.
3.
In auto-request mode, transfer begins when NMIF and TE are all 0 and the DE and DME bits are
set to 1.
DREQ = level detection in burst mode (external request) or cycle-steal mode.
DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 13.2 DMA Transfer Flowchart
Rev. 4.00 Sep. 14, 2005 Page 425 of 982
REJ09B0023-0400