SH7641 Datasheet, PDF (800/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 20 USB Function Module
20.3.1 USB Interrupt Flag Register 0 (USBIFR0)
Together with USB interrupt flag registers 1 (USBIFR1) and 2 (USBIFR2), USBIFR0 indicates
interrupt status information required by the application. When an interrupt occurs, the
corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the
combination with USB interrupt enable register 0 (USBIER0). Clearing is performed by writing 0
to the bit to be cleared, and 1 to the other bits. However, EP1 FULL and EP2 EMPTY are status
bits, and cannot be cleared.
USBIFR0 is initialized to H'10 by a power-on reset.
Initial
Bit
Bit Name Value R/W Description
7
BRST
0
R/W Bus Reset
Set to 1 when the bus reset signal is detected on the
USB bus.
6
EP1FULL 0
R
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data normally from the host, and holds a value of 1 as
long as there is valid data in the FIFO buffer. EP1
FULL is a status bit, and cannot be cleared.
5
EP2TR
0
R/W EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
4
EP2EMPTY 1
R
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written. EP2 EMPTY is a status bit, and cannot be
cleared.
3
SETUPTS 0
R/W Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives normally
a setup command requiring decoding on the
application side, and returns an ACK handshake to
the host.
Rev. 4.00 Sep. 14, 2005 Page 750 of 982
REJ09B0023-0400