SH7641 Datasheet, PDF (201/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 4 Clock Pulse Generator (CPG)
4.5 Changing the Frequency
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are
controlled by software through the frequency control register. The methods are described below.
4.5.1 Changing the Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
WDT. The following must be set:
WTCSR register TME bit = 0: WDT stops
WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock
WTCNT counter: Initial counter value
3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the
IFC[1:0] and PFC[1:0] bits.
4. The processor pauses temporarily and the WDT starts incrementing. The internal and
peripheral clocks both stop and the WDT is supplied with the clock. The clock will continue to
be output at the CKIO pin. This state is the same as the standby state. Whether or not registers
are initialized depends on the module. For details, see table 6.3, Register States in Standby
Mode in section 6, Power-Down Modes.
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
operating again. The WDT stops after it overflows.
4.5.2 Changing the Division Ratio
Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is
not.
1. In the initial state, IFC[1:0] = B'00 and PFC[1:0] = B'11
2. Set the desired value in the IFC[1:0] and PFC[1:0] bits. The values that can be set are limited
by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is
set, the processor will malfunction.
3. The clock is immediately supplied at the new division ratio.
Rev. 4.00 Sep. 14, 2005 Page 151 of 982
REJ09B0023-0400