SH7641 Datasheet, PDF (255/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
9.3 Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations.
9.3.1 Resets
Power-On Reset:
• Conditions
Power-on reset is request
• Operations
Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
Manual Reset:
• Conditions
Manual reset is request
• Operations
Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
H-UDI Reset:
• Conditions
The H-UDI reset command is entered (See section 15.4.4, H-UDI Reset.)
• Operations
Set EXPEVT to H'000, initialize the VBR and SR, and branch to the PC H'A0000000.
The VBR register is set to H'00000000 by initialization. For the SR, the BL and RB bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to 1111.
Initialize the CPU and on-chip peripheral modules. For details, refer to the register descriptions
in the relevant sections.
Rev. 4.00 Sep. 14, 2005 Page 205 of 982
REJ09B0023-0400