SH7641 Datasheet, PDF (281/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)
IMCR0 to IMCR10 are 8-bit writable registers that clear the mask settings for the IRQ and on-
chip peripheral module interrupts. Table 10.4 shows the relationship between IMCR and each
interrupt source.
Initial
Bit
Bit Name Value R/W Description
7
IMC7

W Interrupt Mask Clear
6
IMC6

W Table 10.4 lists the correspondence between the
5
IMC5

W ^{interrupt sources and interrupt mask clear registers.}
4
IMC4

W ^{IMCn (Write)}
3
IMC3

W ^{1: The corresponding bit in interrupt mask register}
IMCn is cleared
2
IMC2

W
0: No processing
1
IMC1

W
n = 7 to 0
0
IMC0

W
Rev. 4.00 Sep. 14, 2005 Page 231 of 982
REJ09B0023-0400