SH7641 Datasheet, PDF (283/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.4 Interrupt Sources
There are four types of interrupt sources: NMI, H-UDI, IRQ, and on-chip peripheral modules.
Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0
masks an interrupt, so the interrupt request is ignored.
10.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. When the BL bit in the status register (SR)
is 0, NMI interrupts are accepted. NMI interrupts are edge-detected. In sleep or standby mode, the
interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt
control register 0 (ICR0) is used to select either rising or falling edge detection.
When using edge-input detection for NMI interrupts, a pulse width of at least two Pφ cycles
(peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt
mask level bits (I3 to I0) in the status register (SR).
It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt.
10.4.2 H-UDI Interrupt
The H-UDI interrupt is accepted between one instruction and another when the H-UDI interrupt
command (section 15.4.5, H-UDI Interrupt.) is entered, the SR interrupt mask bit is set to the
value smaller than 15, and the BL bit in SR is set to 0.
The H-UDI interrupt allows the PC to be saved to the SPC immediately after accepting the
interrupt instruction. The SR at the time of the interrupt acceptation is saved to the SSR. The
INTEVT2 is set to H'5E0. The BL and RB bits in SR are set to 1 and branched to VBR + H'0600.
10.4.3 IRQ Interrupts
IRQ interrupts are input by level or edge from pins IRQ7 to IRQ0. The priority can be set by
interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When ICR1 and ICR3 are overwritten, IRQ interrupts may be mistakenly detected, depending on
the IRQ pin level. To prevent this, overwrite the register while interrupts are masked, then release
the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
Rev. 4.00 Sep. 14, 2005 Page 233 of 982
REJ09B0023-0400