SH7641 Datasheet, PDF (561/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 17 Compare Match Timer (CMT)
17.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables interrupts or DMA
transfer requests, and selects the counter input clock.
CMCSR is initialized to H'0000 by a power on reset, but is not initialized in standby mode.
Bit
15 to 8
Bit Name

7
CMF
6

5
CMR1
4
CMR0
3, 2

Initial
value
All 0
0
0
0
0
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
When 0 is written to CMF after reading CMF = 1
1: CMCNT and CMCOR values match
R Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Compare Match Request
R/W These bits enable or disable DMA transfer request or
interrupt request generation when a compare match
occurs.
00: DMA transfer request/interrupt request disabled
01: DMA transfer request enabled
10: Interrupt request enabled
11: Reserved (Setting prohibited)
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Sep. 14, 2005 Page 511 of 982
REJ09B0023-0400