SH7641 Datasheet, PDF (57/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

1.2 Block Diagram
The block diagram of this LSI is shown in figure1.1.
Section 1 Overview
X/Y
Memory
U Memory
CACHE
BSC
External Bus
Interface
SH3
CPU
DSP
UBC
AUD
INTC
CPG/
WDT
DMAC
I/O port
USB
CMT
MTU
SCIF
ADC
H-UDI
IIC2
[Legend]
ADC:
A/D converter
AUD:
Advanced user debugger
BSC:
Bus state controller
CACHE: Cache memory
CMT:
Compare match timer
CPG/WDT: Clock Pulse generator/Watch dog Timer
CPU:
Central processing unit
DMAC: Direct memory access controller
DSP: Digital signal processor
H-UDI: User debugging interface
INTC: Interrupt controller
SCIF: Serial communication interface
UBC: User break controller
MTU: Multi-Function Timer Pulse unit
USB : USB function module
IIC2: I²C bus interface
Figure 1.1 Block Diagram
Rev. 4.00 Sep. 14, 2005 Page 7 of 982
REJ09B0023-0400