SH7641 Datasheet, PDF (36/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Figure 18.53 Example of Output Phase Switching by Means of UF, VF,
WF Bit Settings (2) ............................................................................................... 615
Figure 18.54 Count Timing in Internal Clock Operation............................................................ 619
Figure 18.55 Count Timing in External Clock Operation .......................................................... 619
Figure 18.56 Count Timing in External Clock Operation (Phase Counting Mode).................... 620
Figure 18.57 Output Compare Output Timing (Normal Mode/PWM Mode)............................. 620
Figure 18.58 Output Compare Output Timing (Complementary PWM Mode/
Reset Synchronous PWM Mode).......................................................................... 621
Figure 18.59 Input Capture Input Signal Timing........................................................................ 621
Figure 18.60 Counter Clear Timing (Compare Match) .............................................................. 622
Figure 18.61 Counter Clear Timing (Input Capture) .................................................................. 622
Figure 18.62 Buffer Operation Timing (Compare Match) ......................................................... 623
Figure 18.63 Buffer Operation Timing (Input Capture) ............................................................. 623
Figure 18.64 TGI Interrupt Timing (Compare Match) ............................................................... 624
Figure 18.65 TGI Interrupt Timing (Input Capture) ................................................................... 624
Figure 18.66 TCIV Interrupt Setting Timing.............................................................................. 625
Figure 18.67 TCIU Interrupt Setting Timing.............................................................................. 625
Figure 18.68 Timing for Status Flag Clearing by the CPU ........................................................ 626
Figure 18.69 Timing for Status Flag Clearing by DMA Activation ........................................... 626
Figure 18.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 627
Figure 18.71 Conflict between TCNT Write and Clear Operations ........................................... 628
Figure 18.72 Conflict between TCNT Write and Increment Operations.................................... 629
Figure 18.73 Conflict between TGR Write and Compare Match ............................................... 630
Figure 18.74 Conflict between Buffer Register Write and Compare Match (Channel 0)........... 631
Figure 18.75 Conflict between Buffer Register Write and Compare Match
(Channels 3 and 4) ................................................................................................ 631
Figure 18.76 Conflict between TGR Read and Input Capture.................................................... 632
Figure 18.77 Conflict between TGR Write and Input Capture................................................... 633
Figure 18.78 Conflict between Buffer Register Write and Input Capture .................................. 634
Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection...... 635
Figure 18.80 Counter Value during Complementary PWM Mode Stop .................................... 636
Figure 18.81 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode............. 637
Figure 18.82 Reset Sync PWM Mode Overflow Flag ................................................................ 638
Figure 18.83 Conflict between Overflow and Counter Clearing ................................................ 639
Figure 18.84 Conflict between TCNT Write and Overflow ....................................................... 639
Figure 18.85 Error Occurrence in Normal Mode, Recovery in Normal Mode........................... 644
Figure 18.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 1........................... 645
Figure 18.87 Error Occurrence in Normal Mode, Recovery in PWM Mode 2........................... 646
Figure 18.88 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode .............. 647
Figure 18.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode ... 648
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