SH7641 Datasheet, PDF (253/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
If multiple general exceptions occur simultaneously in the same instruction, the priority is
determined as follows.
1. A processing-completion type exception generated at the previous instruction*
2. A user break before instruction execution (re-execution type)
3. An exception related to an instruction fetch (CPU address error: re-execution type)
4. An exception caused by an instruction decode (General illegal instruction exceptions and slot
illegal instruction exceptions: re-execution type, unconditional trap: processing-completion
type)
5. An exception related to data access (CPU address error: re-execution type)
6. Unconditional trap (processing-completion type)
7. A user break other than one before instruction execution (processing-completion type)
8. DMA address error
Note: If a processing-completion type exception is accepted at an instruction, exception
processing starts before the next instruction is executed. This exception processing
executed before an exception generated at the next instruction is detected.
Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all
exception requests being processed.
Rev. 4.00 Sep. 14, 2005 Page 203 of 982
REJ09B0023-0400