SH7641 Datasheet, PDF (902/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 23 I/O Ports
23.5.1 Register Description
Port E has the following register.
• Port E data register (PEDR)
23.5.2 Port E Data Register (PEDR)
PEDR is a 16-bit readable/writable register that stores data for pins PTE15 to PTE0. The PEDR is
initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in
standby mode, or in sleep mode.
Initial
Bit
Bit Name Value R/W Description
15
PE15DT 0
14
PE14DT 0
13
PE13DT 0
12
PE12DT 0
11
PE11DT 0
10
PE10DT 0
R/W Bits PE15DT to PE0DT correspond to pins PTE15 to
R/W ^{PTE0. When the pin function is general output port, the}
value of the corresponding PEDR bit in PEDR is
R/W _{returned directly by reading the port. When the function}
R/W ^{is general input port, the corresponding pin level is read}
by reading the port. Table 23.5 shows the function of
R/W _PEDR.
R/W
9
PE9DT
0
R/W
8
PE8DT
0
R/W
7
PE7DT
0
R/W
6
PE6DT
0
R/W
5
PE5DT
0
R/W
4
PE4DT
0
R/W
3
PE3DT
0
R/W
2
PE2DT
0
R/W
1
PE1DT
0
R/W
0
PE0DT
0
R/W
Rev. 4.00 Sep. 14, 2005 Page 852 of 982
REJ09B0023-0400