SH7641 Datasheet, PDF (352/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 12 Bus State Controller (BSC)
Bit
Bit Name
17
BW1
16
BW0
15 to 11 
10
W3
9
W2
8
W1
7
W0
Initial
Value
0
0
All 0
1
0
1
0
R/W Description
R/W Number of Burst Wait Cycles
R/W Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Access Wait Cycles
R/W Specify the number of wait cycles to be inserted in the
R/W ^{first access cycle.}
R/W ^{0000: No cycle}
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Reserved (Setting prohibited)
Rev. 4.00 Sep. 14, 2005 Page 302 of 982
REJ09B0023-0400