SH7641 Datasheet, PDF (254/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
Table 9.1 Exception Event Vectors
Exception Current
Type
Instruction
Exception Event
Exception Process Vector Vector
Priority*¹ Order
at BL=1 Code Offset
Reset
Aborted
Power-on reset
1
1
Reset H'A00 
Manual reset
1
2
Reset H'020 —
H-UDI reset
1
1
Reset H'000 —
General Re-executed User break
2
0
exception
(before instruction execution)
events
CPU address error
2
1
(instruction access) *⁴
Ignored H'1E0 H'00000100
Reset H'0E0 H'00000100
Illegal general instruction exception 2
2
Reset H'180 H'00000100
Illegal slot instruction exception
2
2
Reset H'1A0 H'00000100
CPU address error (data access)*⁴ 2
3
Reset
H'0E0/ H'00000100
H'100
Completed
Unconditional trap
(TRAPA instruction)
2
4
Reset H'160 H'00000100
User breakpoint
2
5
(After instruction execution, address)
Ignored H'1E0 H'00000100
General
exception
events
Completed
User breakpoint
(Data break, I-BUS break)
DMA address error
2
5
2
6
Ignored H'1E0 H'00000100
Retained H'5C0 H'00000100
General
interrupt
requests
Completed
Interrupt requests
3
—*²
Retained —*³ H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
2. For details on priorities in multiple interrupt sources, refer to section 10, Interrupt
Controller (INTC).
3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The
interrupt source code is specified in interrupt source register 2 (INTEVT2). For details,
refer to section 10, Interrupt Controller (INTC).
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
and vector offset are specified.
Rev. 4.00 Sep. 14, 2005 Page 204 of 982
REJ09B0023-0400