SH7641 Datasheet, PDF (170/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 3 DSP Operation
Note: Data transfer by an LDS or STS instruction is possible since DSR is defined as a system
register.
Pointer (R2, R3, R4, R5)
LAB [31:0]
–2, 0, +2, +R8
Any memory areas
LDB [15:0]
X0
Y0
X1
Y1
A0
M0
A1
M1
A0G A1G DSR
Not affected for store and cleared for load
See description of A0G and A1G.
Cannot be specified
Figure 3.15 Single Data-Transfer Operation Flow (Word)
Rev. 4.00 Sep. 14, 2005 Page 120 of 982
REJ09B0023-0400