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SH7641 Datasheet, PDF (35/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series
Figure 18.20 Example of PWM Mode Setting Procedure .......................................................... 578
Figure 18.21 Example of PWM Mode Operation (1) ................................................................. 578
Figure 18.22 Example of PWM Mode Operation (2) ................................................................. 579
Figure 18.23 Example of PWM Mode Operation (3) ................................................................. 580
Figure 18.24 Example of Phase Counting Mode Setting Procedure........................................... 582
Figure 18.25 Example of Phase Counting Mode 1 Operation .................................................... 582
Figure 18.26 Example of Phase Counting Mode 2 Operation .................................................... 583
Figure 18.27 Example of Phase Counting Mode 3 Operation .................................................... 584
Figure 18.28 Example of Phase Counting Mode 4 Operation .................................................... 585
Figure 18.29 Phase Counting Mode Application Example......................................................... 587
Figure 18.30 Procedure for Selecting the Reset-Synchronized PWM Mode.............................. 589
Figure 18.31 Reset-Synchronized PWM Mode Operation Example
(When the TOCR's OLSN = 1 and OLSP = 1) ..................................................... 590
Figure 18.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode .................. 593
Figure 18.33 Example of Complementary PWM Mode Setting Procedure................................ 594
Figure 18.34 Complementary PWM Mode Counter Operation.................................................. 596
Figure 18.35 Example of Complementary PWM Mode Operation ............................................ 597
Figure 18.36 Example of PWM Cycle Updating........................................................................ 600
Figure 18.37 Example of Data Update in Complementary PWM Mode .................................... 601
Figure 18.38 Example of Initial Output in Complementary PWM Mode (1)............................. 602
Figure 18.39 Example of Initial Output in Complementary PWM Mode (2)............................. 603
Figure 18.40 Example of Complementary PWM Mode Waveform Output (1) ......................... 605
Figure 18.41 Example of Complementary PWM Mode Waveform Output (2) ......................... 606
Figure 18.42 Example of Complementary PWM Mode Waveform Output (3) ......................... 607
Figure 18.43 Example of Complementary PWM Mode 0% and
100% Waveform Output (1).................................................................................. 608
Figure 18.44 Example of Complementary PWM Mode 0% and 100%
Waveform Output (2)............................................................................................ 609
Figure 18.45 Example of Complementary PWM Mode 0% and 100%
Waveform Output (3)............................................................................................ 609
Figure 18.46 Example of Complementary PWM Mode 0% and 100%
Waveform Output (4)............................................................................................ 610
Figure 18.47 Example of Complementary PWM Mode 0% and 100%
Waveform Output (5)............................................................................................ 610
Figure 18.48 Example of Toggle Output Waveform Synchronized with PWM Output............. 611
Figure 18.49 Counter Clearing Synchronized with Another Channel ........................................ 612
Figure 18.50 Example of Output Phase Switching by External Input (1)................................... 613
Figure 18.51 Example of Output Phase Switching by External Input (2)................................... 614
Figure 18.52 Example of Output Phase Switching by Means of UF, VF,
WF Bit Settings (1) ............................................................................................... 614
Rev. 4.00 Sep. 14, 2005 Page xxxv of l