SH7641 Datasheet, PDF (497/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
• Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more)
• External wait mask specification (WM = 0).
In addition to the above conditions, the following conditions are included depending on the
detection method of DREQ.
• For DREQ level detection: only write access
• For DREQ edge detection: both write access and read access
Phenomenon: The detection timings of the DREQ pin in the above access are shown in figures
13.19 to 13.22.
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CPU
1st acceptance
Non-sensitive period
DMAC write or read
2nd acceptance
Non-sensitive period
3rd acceptance possible
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 4 by Idle Cycles
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CPU
1st acceptance
DMAC write or read
2nd acceptance
Non-sensitive period
Non-sensitive period
3rd acceptance is after the
next DACK assertion
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 2 by Idle Cycles
Rev. 4.00 Sep. 14, 2005 Page 447 of 982
REJ09B0023-0400