SH7641 Datasheet, PDF (270/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
Figure 10.1 shows a block diagram of the INTC.
NMI
IRQ7 to IRQ0
DMAC
SCIF0 to 2
ADC
USB
CMT0 and CMT1
MTU0 to MTU4
WDT
H-UDI
IIC2
I/O
controller
8
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR
IRR0
IPR
IMR
IMCR
Bus
interface
[Legend]
DMAC: DMA controller
SCIF: Serial communication interfaces (with FIFO) 0 to 2
ADC: A/D converter
USB: USB funciton module
CMT: Compare match timers 0 and 1
MTU: Multifuncton timer pulse units 0 to 4
WDT: Watchdog timer
H-UDI: User debugging interface
Interrupt contoroller
IIC2: I²C interface 2
ICR: Interrupt control register
IPR: Interrupt priority registers B to J
IMR: Interrupt mask registers 0 to 10
IMCR: Interrupt mask clear registers 0 to 10
IRR0: Interrupt request register 0
SR: Status register
Figure 10.1 Block Diagram of INTC
Rev. 4.00 Sep. 14, 2005 Page 220 of 982
REJ09B0023-0400