SH7641 Datasheet, PDF (248/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
9.1 Register Descriptions
There are three registers for exception handling. A register with an undefined initial value should
be initialized by the software.
• TRAPA exception register (TRA)
• Exception event register (EXPEVT)
• Interrupt event register 2 (INTEVT2)
Figure 9.1 shows the bit configuration of each register.
31
0
31
0
31
0
10 9
21 0
TRA 0
12 11
0
EXPEVT
TRA
EXPEVT
12 11
INTEVT2
0
INTEVT2
Figure 9.1 Register Bit Configuration
9.1.1 TRAPA Exception Register (TRA)
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Initial
Bit
Bit Name Value R/W
31 to 10 

R
9 to 2
1, 0
TRA


R/W

R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-Bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 198 of 982
REJ09B0023-0400