SH7641 Datasheet, PDF (732/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 18 Multi-Function Timer Pulse Unit (MTU)
2. Low-Level Detection
Figure 18.116 shows the low-level detection operation. Sixteen continuous low levels are
sampled with the sampling clock established by the ICSR1. If even one high level is detected
during this interval, the low level is not accepted.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
Pφ
Sampling
clock
8/16/128 clock
cycles
POE input
TIOC3B/
PTE[6]
Hi-Z state*
When low level is
Flag set
sampled at all points
1
2
3
16 _{(POE received)}
When high level is
sampled at least once
1
2
13 Flag not set
Note: * Other high-current pins (TIOC3D/PTE[4], TIOC4A/PTE[3], TIOC4B/PTE[2], TIOC4C/PTE[1],
and TIOC4D/PTE[0]) also become the Hi-Z state at the same timing.
Figure 18.116 Low-Level Detection Operation
Output-Level Compare Operation: Figure 18.117 shows an example of the output-level
compare operation for the combination of TIOC3B/PTE[6] and TIOC3D/PTE[4]. The operation is
the same for the other pin combinations.
Pφ
TIOC3B/
PTE[6]
TIOC3D/
PTE[4]
0 level overlapping detected
Hi-Z
Figure 18.117 Output-Level Detection Operation
Rev. 4.00 Sep. 14, 2005 Page 682 of 982
REJ09B0023-0400