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SH7641 Datasheet, PDF (128/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series | |||
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Section 2 CPU
System Control Instructions
Table 2.24 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC Rm,SSR
LDC Rm,SPC
LDC Rm,R0_BANK
LDC Rm,R1_BANK
LDC Rm,R2_BANK
LDC Rm,R3_BANK
LDC Rm,R4_BANK
LDC Rm,R5_BANK
LDC Rm,R6_BANK
LDC Rm,R7_BANK
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,
R0_BANK
LDC.L @Rm+,
R1_BANK
LDC.L @Rm+,
R2_BANK
LDC.L @Rm+,
R3_BANK
Instruction Code
0000000000101000
0000000001001000
0000000000001000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00111110
0100mmmm01001110
0100mmmm10001110
0100mmmm10011110
0100mmmm10101110
0100mmmm10111110
0100mmmm11001110
0100mmmm11011110
0100mmmm11101110
0100mmmm11111110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00110111
0100mmmm01000111
0100mmmm10000111
0100mmmm10010111
0100mmmm10100111
0100mmmm10110111
Operation
0 â MACH, MACL
0âS
0âT
Rm â SR
Rm â GBR
Rm â VBR
Rm â SSR
Rm â SPC
Rm â R0_BANK
Rm â R1_BANK
Rm â R2_BANK
Rm â R3_BANK
Rm â R4_BANK
Rm â R5_BANK
Rm â R6_BANK
Rm â R7_BANK
(Rm) â SR, Rm + 4 â Rm
(Rm) â GBR, Rm + 4 â Rm
(Rm) â VBR, Rm + 4 â Rm
(Rm) â SSR, Rm + 4 â Rm
(Rm) â SPC, Rm + 4 â Rm
(Rm) â R0_BANK,
Rm + 4 â Rm
(Rm) â R1_BANK,
Rm + 4 â Rm
(Rm) â R2_BANK,
Rm + 4 â Rm
(Rm) â R3_BANK,
Rm + 4 â Rm
Execution
States T Bit
1
â
1
â
1
0
6
LSB
4
â
4
â
4
â
4
â
4
â
4
â
4
â
4
â
4
â
1
â
4
â
4
â
8
LSB
4
â
4
â
4
â
4
â
4
â
4
â
4
â
4
â
Rev. 4.00 Sep. 14, 2005 Page 78 of 982
REJ09B0023-0400
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