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SH7641 Datasheet, PDF (320/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series
Section 12 Bus State Controller (BSC)
 Supports low-frequency and power-down modes.
 Issues MRS and EMRS commands.
6. Byte-selection SRAM interface
 Can connect directly to a byte-selection SRAM
7. Burst MPX-IO interface
 Can connect directly to a peripheral LSI that needs an address/data multiplexing.
 Supports burst transfer
8. Burst ROM interface (clock synchronous)
 Can connect directly to a ROM of the clock synchronous type
9. Bus arbitration
 Shares all of the resources with other CPU and outputs the bus enable after receiving the
bus request from external devices.
10. Refresh function
 Supports the auto-refresh and self-refresh functions.
 Specifies the refresh interval using the refresh counter and clock selection
 Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8)
Rev. 4.00 Sep. 14, 2005 Page 270 of 982
REJ09B0023-0400