SH7641 Datasheet, PDF (200/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 4 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
11, 10 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
STC1
0
R/W Frequency multiplication ratio of PLL circuit 1
8
STC0
0
R/W 00: × 1 time
01: × 2 times
10: × 3 times
11: × 4 times
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
5
IFC1
0
R/W Internal Clock Frequency Division Ratio
4
IFC0
0
R/W These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
3, 2

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
PFC1
1
R/W Peripheral Clock Frequency Division Ratio
0
PFC0
1
R/W These bits specify the division ratio of the peripheral
clock frequency with respect to the output frequency
of PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
Rev. 4.00 Sep. 14, 2005 Page 150 of 982
REJ09B0023-0400