SH7641 Datasheet, PDF (767/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of
transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with
the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is initialized to H'0000 by a
power on reset.
Bit
Bit Name
15 to 13 —
12
T4
11
T3
10
T2
9
T1
8
T0
7 to 5 —
4
R4
3
R3
2
R2
1
R1
0
R0
Initial
value
All 0
0
0
0
0
0
All 0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R T4 to T0 bits indicate the quantity of non-transmitted
R
data stored in SCFTDR. H'00 means no transmit data,
and H'10 means that SCFTDR is full of transmit data.
R
R
R
R Reserved
These bits are always read as 0. The write value should
always be 0.
R R4 to R0 bits indicate the quantity of receive data
R
stored in SCFRDR. H'00 means no receive data, and
H'10 means that SCFRDR full of receive data.
R
R
R
19.3.11 Serial Port Register (SCSPTR)
The serial port register (SCSPTR) controls input/output and data of pins multiplexed to SCIF
function. Bits 1 and 0 can input data from RxD pin and output data to TxD pin, so they control
break of serial transmitting/receiving. Bits 3 and 2 can control input/output data of SCK pin, bits 5
and 4 can control input/output data of CTS pin, and bits 7 and 6 can control input/output data of
RTS pin.
The CPU can always read and write to SCSPTR. SCSPTR is initialized to H'0050 by a power-on
reset.
Rev. 4.00 Sep. 14, 2005 Page 717 of 982
REJ09B0023-0400