SH7641 Datasheet, PDF (265/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 9 Exception Handling
CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat
control period, the exception is accepted but an exception code (H'070) indicating the repeat loop
period is specified in the EXPEVT. If a CPU address error occurs in instructions following a
repeat detection instruction to repeat end instruction, an exception code for instruction access or
data access is specified in the EXPEVT.
The SPC is saved according to the SPC Saved by an Exception in Repeat Control Period
description in section 9.4.2, Exception in Repeat Control Period.
After the CPU address error exception processing, the repeat control cannot be returned correctly.
To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the
repeat control period.
Note:
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
Table 9.6 Instruction Where a Specific Exception Occurs When a Memory Access
Exception Occurs in Repeat Control
Instruction Where an
Exception Occurs
1
Number of Instructions in a Repeat Loop
2
3
4 or Greater
RptDtct
RptDtct1
Instruction/data Instruction/data Instruction/data Instruction/data
access
access
access
access
RptDtct2

Instruction/data Instruction/data Instruction/data
access
access
access
RptDtct3


Instruction/data Instruction/data
access
access
Note:
The following labels are used here.
RptDtct: Repeat detection instruction address
RptDtct1: An instruction address one instruction following the repeat detection instruction
RptDtct2: An instruction address two instruction following the repeat detection instruction
RptDtct3: An instruction address three instruction following the repeat detection instruction
Rev. 4.00 Sep. 14, 2005 Page 215 of 982
REJ09B0023-0400