SH7641 Datasheet, PDF (245/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 8 X/Y Memory
8.4 X/Y Memory Access from DMAC
The X/Y memory can be accessed by the DMAC via the I bus. Use the addresses
between H'05007000 and H'05008FFF or H'05017000 and H'05018FFF.
8.5 Usage Note
When accessing the X/Y memory from the CPU and DSP, if the cache is on, access must be
performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be
guaranteed. When the cache is off, spaces P0 and P2 can both be used. Specify the P2 area for
parallel operation and double data transfer. (See section 3.1.9, Data Transfer Operation.)
8.6 Sleep Mode
In sleep mode, the X/Y memory is not accessed from the I bus master module such as DMAC.
8.7 Address Error
When an address error in write access to the X/Y memory occur, the contents of the X/Y memory
may be corrupted.
Rev. 4.00 Sep. 14, 2005 Page 195 of 982
REJ09B0023-0400