SH7641 Datasheet, PDF (207/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 5 Watchdog Timer (WDT)
5.2.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
composed of bits to select the clock used for the count, overflow flags, and timer enable bit. The
WTCSR register holds its value in an internal reset due to WDT overflow. The WTCSR register is
initialized to H'00 only by a power-on reset caused by the RESETP pin.
When used to count the clock settling time for canceling a standby, it retains its value after counter
overflow. Use a word access to write to the WTCSR counter, writing H'A5 in the upper byte. Use
a byte access to read the WTCSR.
Note: The WTCNT differs from other registers in the prevention of erroneous writes.
See section 5.2.3, Notes on Register Access, for details.
Initial
Bit
Bit Name Value R/W Description
7
TME
0
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in standby mode or when
changing the clock frequency.
0: Timer disabled: Count-up stops and WTCNT value
is retained
1: Timer enabled
6
WT/IT
0
R/W Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Use as interval timer
1: Use as watchdog timer
Note: If WT/IT is modified when the WDT is running,
the up-count may not be performed correctly.
5
RSTS
0
R/W Reset Select
Selects the type of reset when the WTCNT overflows
in watchdog timer mode. In interval timer mode, this
setting is ignored.
0: Power-on reset
1: Manual reset
Rev. 4.00 Sep. 14, 2005 Page 157 of 982
REJ09B0023-0400