SH7641 Datasheet, PDF (290/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 10 Interrupt Controller (INTC)
10.5.2 Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT2. The code in
INTEVT2 can be used as an offset for branching to the specific handler.
2. Clear the interrupt source in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4. Figure 10.2 shows a sample interrupt
operation flowchart.
10.6 Notes on Use
10.6.1 Notes on USB Bus Power Control
Use IRQ0/IRQ1 carefully. The USB bus power control uses the interrupt control logic block for
IRQ0/IRQ1.
For the details about the USB bus power control, refer to section 20, USB Function Module.
10.6.2 Timing to Clear an Interrupt Source
As described in section 10.5.1, Interrupt Sequence, clear the interrupt source flags in the interrupt
handler.
To avoid accepting an interrupt source flag that has been cleared, read the flag and then, execute
the RTE instruction.
Rev. 4.00 Sep. 14, 2005 Page 240 of 982
REJ09B0023-0400