SH7641 Datasheet, PDF (305/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 11 User Break Controller (UBC)
11.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers
have a queue structure and a stored register is shifted at every branch.
Bit
Bit Name
31
DVF
30 to 28 
27 to 0 BDA27 to
BDA0
Initial
Value
0
All 0

R/W Description
R
BRDR Valid Flag
Indicates whether a branch destination address is
stored. When a branch destination address is fetched,
this flag is set to 1. This flag is cleared to 0 by reading
BRDR.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
Rev. 4.00 Sep. 14, 2005 Page 255 of 982
REJ09B0023-0400