SH7641 Datasheet, PDF (491/1036 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7641 Series

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
CPU
1st acceptance
2nd acceptance
Non sensitive period
Acceptance start
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
1st acceptance
Non sensitive period
CPU
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
CPU
2nd acceptance
Acceptance
start
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO
Bus cycle
CPU
CPU
DMAC
DMAC
DREQ
DACK
Non sensitive period
Burst acceptance
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection
Rev. 4.00 Sep. 14, 2005 Page 441 of 982
REJ09B0023-0400